In receivers of radio communication systems utilizing quadrature modulation, four-phase clock signals having 0 degrees, 90 degrees, 180 degrees, and 270 degrees are generated and supplied to a mixer circuit in order to perform quadrature modulation with respect to an in-phase component and a quadrature-phase component. For the purpose of generating even-number clock signals such as four-phase clock signals, generally, an oscillating frequency that is even-number times (i.e., four times in the case of four phases) as high as a desired frequency is generated and divided to produce clock signals having the desired frequency. In the case of four phases, four consecutive cycles of the oscillating signal having the base frequency corresponds to the 0-degree phase, 90-degree phase, 180-degree phase, and 270-degree phase of a frequency-divided signal having ¼ the frequency. These four-phase clock signals can thus be easily generated.
The above-described scheme that generates an oscillating signal having even-number times a desired frequency gives rise to a problem in that electrical current consumption increases due to the use of high-frequency signals. Further, the generation of accurate high-frequency signals may involve using LCVCO (LC-oscillator-based voltage controlled oscillator), which uses an LC oscillator having an inductor and a capacitor. An LCVCO may be produced by use of a special manufacturing process and large circuit size. This gives rise to a problem in that the use of such a LCVCO results in a cost increase compared to the use of a VCO (.e., ring VCO) utilizing a ring oscillator circuit.
A ring VCO that is favorable from a cost point of view is generally comprised of odd-number inverters in order to induce oscillation. Even-number phases are produced by using a ring oscillator circuit comprised of even-number inverters. Such a ring oscillator circuit having even-number stages, however, does not oscillate on its own. In consideration of this, provision may be made such that two nodes having a 180-degree phase difference with each other are connected to the respective ends of a latch. With this provision, these two nodes are forced to change to the opposite phases at the same time.
[Patent Document 1] Japanese Laid-open Patent Publication No. 8-265108
[Patent Document 2] Japanese Laid-open Patent Publication No. 2007-189614
[Non-Patent Document 1] A. Maxim, R. Johns, S. Dupue, “0.13μ CMOS Hybrid TV Tuner Using a Calibrated Image and Harmonic Rejection Mixer,” 2007 Symposium on VLSI Circuits Digest of Technical Papers, pp. 206-207